The present invention relates generally to semiconductor manufacturing and, more particularly, to the use of a feature to provide stress uniformity.
Integrated circuits comprise a large number of individual circuit elements, such as transistors, capacitors and resistors and the like. These elements are connected internally to form complex circuits, such as memory devices, logic devices and microprocessors. The performance of integrated circuits can be improved by increasing the number of functional elements in the circuit to increase its functionality and/or by increasing the speed of operation of the circuit elements. A reduction of feature sizes allows the formation of a greater number of circuit elements on the same area, hence allowing an extension of the functionality of the circuit, and also reduces signal propagation delays, thus making an increase of the speed of operation of circuit elements possible.
Field effect transistors are commonly used as switching elements in integrated circuits. They allow control of a current flowing through a channel region located between a source region and a drain region. The source region and the drain region are highly doped. In N-type transistors, the source and drain regions are doped with an N-type dopant. Conversely, in P-type transistors, the source and drain regions are doped with a P-type dopant. The doping of the channel region is inverse to the doping of the source region and the drain region. The conductivity of the channel region is controlled by a gate voltage applied to a gate electrode formed above the channel region and separated therefrom by a thin insulating layer. Depending on the gate voltage, the channel region may be switched between a conductive “on” state and a substantially non-conductive “off” state.
When reducing the size of field effect transistors, it is important to maintain a high conductivity of the channel region in the “on” state. The conductivity of the channel region in the “on” state depends on the dopant concentration in the channel region, the mobility of the charge carriers, the extension of the channel region in the width direction of the transistor and the distance between the source region and the drain region, which is commonly denoted as “channel length.” While a reduction of the width of the channel region leads to a decrease of the channel conductivity, a reduction of the channel length enhances the channel conductivity. An increase of the charge carrier mobility leads to an increase of the channel conductivity.
As feature sizes are reduced, the extension of the channel region in the width direction is also reduced. A reduction of the channel length raises a number of issues associated that need to be addressed. First, advanced techniques of photolithography and etching have to be provided to reliably and reproducibly create transistors having short channel lengths. Moreover, highly sophisticated dopant profiles, in the vertical direction as well as in the lateral direction, are required in the source/drain regions to provide a low sheet resistivity and a low contact resistivity in combination with a desired channel controllability. Furthermore, a reduction of the channel length may require a reduction in the depth of the source/drain region with respect to the interface formed by the gate insulation layer and the channel region. In some approaches, this may be achieved by forming raised source and drain regions formed with a specified offset to the gate electrode.
In view of the problems associated with a further reduction of the channel length, it has been proposed to also enhance the performance of field effect transistors by increasing the charge carrier mobility in the channel region. In principle, at least two approaches may be used to increase the charge carrier mobility.
First, the dopant concentration in the channel region may be reduced. Thus, the probability of scattering events of charge carriers in the channel region is reduced, which leads to an increase of the conductivity of the channel region. Reducing the dopant concentration in the channel region, however, significantly affects the threshold voltage of the transistor device. This makes the reduction of dopant concentration a less attractive approach.
Second, the lattice structure in the channel region may be modified by creating tensile or compressive stress. This leads to a modified mobility of electrons and holes, respectively. A tensile stress in the channel region increases the mobility of electrons. Depending on the magnitude of the tensile stress, an increase of the electron mobility of up to 20% or more can be achieved. In an N-type transistor, this leads to a corresponding increase of the conductivity of the channel region. Conversely, compressive stress in the channel region may increase the mobility of holes, thereby providing the potential for enhancing the performance of P-type transistors.
In a method of forming field effect transistors having stressed channel regions according to the state of the art, a layer comprising an alloy of silicon and germanium or an alloy of silicon and carbon, respectively, is introduced into the channel region to create a tensile or compressive stress. Alternatively, such a stress-creating layer may be provided below the channel region. In some instances, a portion of the substrate adjacent eth channel is removed and replaced with a stress-inducing silicon alloy. Subsequently, the source and drain regions are formed in the alloy material by further doping procedures.
A problem with the method of forming field effect transistors having stressed channel regions according to the state of the art is that the formation of the stress-creating layer requires a considerable modification of conventional and well-approved techniques used for the formation of field effect transistors. Another issue is that the physical layout of the semiconductor device affects the stress uniformity locally and across the wafer. Because the layout includes regions with differing pattern densities, the induced stresses are not uniform across an individual die. Highly dense active regions may be adjacent other regions with low pattern density. The stress characteristics differ with pattern density. Also, on a local scale, features on the periphery of a particular functional block do not exhibit the same geometry as features within the block. Hence, the local stress at these features also varies.
By way of example, consider the cross-section view of an exemplary semiconductor device 100 shown in FIG. 1. The device 100 includes a plurality of transistors 110A-D formed on an active region of a substrate 115 and separated by isolation structures 120 (e.g., shallow trench isolation structures). For ease of illustration, not all features of the transistors 110A-D are shown. In the illustration of FIG. 1, the transistors 110A-D are N-channel devices. A stress-inducing film 125 is formed over the transistors 110A-D to induce stress in the channel regions 135 to enhance performance. Note that the end transistors 110A, 110D have adjacent regions 140 that have a reduced pattern density. For example, the regions 140 may exist between different structures. Because of the change in pattern density, the stress induced on the channel regions 135 of the transistors 110A, 110D adjacent the regions 140 differs from the stress induced on the channel regions 135 of the center transistors 110B, 110C. The level of stress variation depends on various factors, such as the dimensions and materials with which the transistors 110A-D, substrate 115, and film 125 are fabricated. Stress variation across the collection of transistors can result in performance variation, which can, in turn, reduce the grade and profitability of the device 100.
This section of this document is intended to introduce various aspects of art that may be related to various aspects of the present invention described and/or claimed below. This section provides background information to facilitate a better understanding of the various aspects of the present invention. It should be understood that the statements in this section of this document are to be read in this light, and not as admissions of prior art. The present invention is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above.